Make Utility In Unix
Compiling a program that consists of more than one source file involves two steps: compiling each module into its respective object file and then linking the object files into the executable program. Object files are intermediate code files created by the compiler which by themselves are not executable, but when linked together, are. They are easily identified by their .o extension.Object files are created with the -c option on the compiler. For example, the commands cc -c prog.c cc -c func.c will compile the source files prog.c and func.c into the object files prog.o and func.o.An additional command to the compiler, cc prog.o func.o will compile prog.o and func.o into a working a.out file which you can execute. The process of putting together .o files is called "linking." These are the basic steps for compiling a program with more than one source file.So compiling source code files can be very tedious when it contains several source files and we want to type compile command every time. MAKE allows you to automate this by specifying the compilation commands in a file which MAKE uses, called the "Makefile".The basic idea behind creation of a Makefile is to tell MAKE what you want to compile and how to compile it. A Makefile is a normal text file that may be created with any Unix editor,such as vi. The usual form of a Makefile entry is: target: dependency ... (tab)command (tab)command .... MAKE is very particular about how targets, dependencies, and commands are arranged in Makefile entries. The target should be at the leftmost margin with a colon immediately after it. There should be at least one space or tab between the colon and the first dependency. Dependencies should be separated by spaces or tabs.The command should be on the next immediate line and spaced from the left margin by ONE tab. In general, the Makefile tells MAKE how to do each step of the compilation process. For each .c file, MAKE creates a corresponding .o file. Then when all the .o files have been compiled, MAKE links them together into an executable. Let us continue with an example. We have two source files, prog.c and func.c.The prog.c file has an #include "head.h" statement, the func.c file has no includes,and the executable program is to be named "myprog". One way to construct a Makefile would be as follows: myprog: prog.o func.o cc prog.o func.o -o myprog prog.o: prog.c head.h cc -c prog.c func.o: func.c cc -c func.c This Makefile says that myprog is dependent on prog.o and func.o. That is, prog.o and func.o are required to exist and be up-to-date in order to put together the program myprog. Likewise, prog.o is dependent on prog.c and head.h. Finally func.o is dependent on func.c.We will now use MAKE to create prog.o, func.o, and myprog with the command: % make myprog MAKE looks for a file specifically called "Makefile". If it does not find one,MAKE will not work.MAKE starts at the first target, "myprog". It notes that there is a dependency on prog.o and so proceeds to the target "prog.o". Now MAKE sees that prog.o in turn is dependent upon prog.c and head.h. MAKE then checks to see if prog.c is current. Since there is no prog.c target in the Makefile and prog.c exists,MAKE is satisfied that prog.c is up-to-date. Likewise for head.h. MAKE returns to the business of assuring that prog.o is up-to-date. Since prog.o does not exist,MAKE invokes the command "cc -c prog.c" to make a current prog.o. MAKE returns to "myprog" and continues to the next dependency, func.o. MAKE goes through a sequence of steps to create func.o similar to those described for prog.o. Returning to "myprog", MAKE sees that there are no more dependencies to check. Since "myprog" does not exist, MAKE invokes the command "cc prog.o func.o -o myprog" and the job is done.